The present invention relates to a digital line driver circuit for driving a transmission line, and to a method of operating a digital line driver circuit.
It is well known that when transmitting a signal over a frequency dependent medium like a real transmission line having frequency losses or over an optical cable, the signal shape will change in the course of the transmission. A bandwidth limited electrical transmission line will for example cause higher losses in high frequency components of a transmitted signal than in lower frequency components. The effect of the transmission medium on the signal is the more pronounced the higher the frequency components of the signal to be transmitted is, and the longer the transmission length through the medium is. This effect imposes limits on the maximum transmission length and/or the maximum speed of a signal transmission system having a signal driver at an input side of the transmission medium and a receiver for receiving signal outputs by the transmission medium at the other side.
Modern communication systems use digital signals for carrying information. Generally speaking, a digital signal generally consists of a random sequence of so-called symbols, each representing one or more data bits. When a digital signal is transmitted over a frequency dependent medium like a transmission line, the transmitted digital signal will suffer from the distortion even if there is perfect matching at the receiver side and at the transmitter side, because the higher order harmonics in the signal spectrum suffer from higher losses than lower frequency components of the signal spectrum. Shorter pulses in the digital signal at the receiver side will not reach their full amplitude and the slope of the rising and falling edges in the signal seen by the receiver will deteriorate. This effect, also called inter symbol interference (ISI) imposes limits on the data rate that the receiver will be able to detect.
It is known to increase the limits of the data rate or the transmission length over a given medium by means of pre-distorting the digital signal at the input side of the medium. Broadly speaking, the pre-distortion takes into account the distortion caused by the transmission medium, by means of emphasizing components of the signal to be transmitted that will suffer from loss in the transmission medium. This technique is also known as pre-emphasis.
As disclosed e.g. in DE 198 25 258 A, a conventional way to provide a digital data signal with pre-distortion or pre-emphasis is to delay the digital signal by one bit period or a predetermined fraction of the bit period and to combine the amplitude of the digital signal and the delayed digital signal. From this document an output buffer circuit is known that is able to provide a digital output signal with pre-distortion by means of determining the output signal level depending not only on the current data bit to be transmitted, but also dependent on the history fo the output signal.
U.S. Pat. No. 4,584,690 discloses minimizing the effect of inter symbol interference by provision of digital pre-compensation in the transmitted signal, in order to maximize the slew rate between consecutive bits. From this document, it is known to base the pre-compensation scheme on knowledge of the bit pattern and the amount of energy contained in a sequence of bits.
From IEEE Journal of Solid State Circuits, volume 34, no. 5, May 1999, pages 580 to 585 a so-called full bit pre-distortion combines the amplitudes of the digital data signal with the weighted amplitudes of one or more delayed versions of the digital data signal, each delayed version having a delay of one or more full bit periods relative to the undelayed digital data signal. The number of delayed versions of the digital data signal with different delay that are combined together determine the so-called order of pre-distortion. It is known from this document that partial bit pre-distortion is equally well feasible by means of combining the digital data signal with a delayed version of it, the delay being set to p times to bit period. The typical value of p is 0,5, this being called half bit pre-distortion.
It is to be noted that the term xe2x80x9cbitxe2x80x9d in this context does not necessarily mean a unit of information or a data unit. Rather, in the context of pre-distortion or pre-emphasis this term generally refers to a repetitively at random occurring constant amplitude segment of minimum duration in the digital data signal. In the special case that the digital data signal format is binary providing two symbols represented by two different signals, one representing logical xe2x80x9c0xe2x80x9d and the other level representing logic xe2x80x9c1xe2x80x9d, then a segment of minimum duration have the same duration as a bit period. There exist, however, other well known digital signal formats wherein a segment of minimum duration has a duration different from the duration of an information bit.
It is the object of the present invention to provide an improved driver circuit for outputting digital signals to a transmission line, where said driver circuit provides pre-emphasis capabilities. It is also an object to provide an improved method of operating such a digital line driver circuit.
These objects are achieved by a digital line driver circuit as described in claim 1, and by a method of operating a digital line driver circuit as described in claim 14. Advantageous embodiments are described in the dependent claims.
In accordance with the present invention a digital line driver circuit is provided that receives a digital input signal and outputs a digital output signal in accordance with said input signal, where the digital line driver circuit is operable in at least a first and a second mode. The respective mode is determined by a mode selection signal. In a first mode no pre-emphasis is added to the output signal. The first mode can, for example, be a signal relay mode in which the digital output signal follows the digital input signal. The second mode is a pre-emphasis mode, in which the digital output signal follows the digital input signal, but has an additional pre-distortion.
Therefore, the digital line driver circuit of the present invention can deliver both signals with and without pre-emphasis. A normal signal may simply replicate or directly follow the input signal, whereas a pre-emphasis signal has added distortion. Therefore, the circuit of the present invention provides the advantage of pre-emphasis if necessary for the specific signal being transmitted or the specific prevailing conditions, but is not restricted thereto, and can also output a normal signal if this is necessary or desired. The present invention therefore provides great flexibility.
The digital line driver circuit comprises a signal processing section and an output stage, where the signal processing section receives the digital input signal and outputs control signals to the output stage. Preferably, the signal processing section contains a delay circuit in order to generate appropriate control signals for the pre-emphasis mode. The use of delays for generating pre-emphasis signals is well known, as mentioned in the introduction. However, it may be noted that the control signals for the pre-emphasis mode may be generated in any suitable or appropriate way. The documents mentioned in the introduction to the specification are herewith incorporated by reference.
The output stage is preferably arranged to have an output impedance matched with the transmission medium, e.g. 50 Ohm, for both differential and common mode transmission. Also it is advantageous to provide an internal supply current balancing mechanism that is able to cancel the internal data signal dependent current load variations. This current load balancing mechanism is arranged to work over a large common mode range. It alleviates the need for internal power supplies with low output impedance and reduces the switching transient load such that decoupling capacitors, if any, between the internal power supply lines and ground can be kept small.
The output stage can be arranged to be fed from external power sources, where the number of external power sources can be equal to the number of levels provided in the signals of the pre-emphasis mode. However, it is equally possible to also provide the output stage with a lesser number of external reference voltages, in which case the output circuits itself may generate appropriate reference voltages e.g. with voltage dividers. The latter alternative has the advantage of reducing the number of external components and complexity.